Packet caching is one of the necessary key technologies in modern communication devices. The main purpose of the packet caching is to cache data packets in the event of data traffic congestion, so as to avoid or reduce data loss. With the continuous increase of the communication device speed, packet caching becomes harder and harder, and the main difficulty is in the combination of a large capacity and a high speed.
A basic requirement on high-end routers and other communication devices is to have a packet cache capable of absorbing wire-speed traffic of at least 200 ms. This means in the case of 100 Gbps port speed, the devices need be able to cache at least 20 GB of data. The packet cache also needs to provide a read and write bandwidth that matches the port speed. The port speed of up to 100 Gbps makes it rather difficult for a low-cost, large-capacity Dynamic Random-Access Memory (DRAM) to serve as the packet cache.
For communication devices not requiring such a high caching capacity, like a Layer 2 switch, using an on-chip cache is a simple and low-cost method, where data packets are cached directly in memories inside a chip so as to avoid the extra cost for the use of off-chip memories. With the method, no off-chip memory device controller or connecting pins are needed, so that the complexity and cost of chip design are lower. Moreover, the on-chip cache also provides sufficient read and write bandwidth for such communication devices.
Another method to increase packet caching capacity while providing the required read and write bandwidth is to use off-chip memories. High-speed Static Random-Access Memory (SRAM) or dedicated memories such as Reduced Latency Dynamic Random Access Memory (RLDRAM) are often adopted.
The universal DRAM is cheap and widely used. It has over 1 GB of capacity per chip. The DRAM can provide a large packet cache capacity at a low-cost and with low risks.
During the implementation of the present invention, however, the inventor found that none of the above-described on-chip high-speed caching method, off-chip high-speed caching method and off-chip large-capacity caching method can realize large-capacity, high-speed and low-cost packet caching at the same time. For example, the on-chip caching method normally provides lower than 10 MB of cache capacity, which is not suitable for high-end routers and Layer 3 switches that require high caching capacities. SRAM is expensive and the capacity per chip is limited to below 72 MB. Dedicated memories are also expensive and subject to supply risks. The universal DRAM has a low read and write efficiency so that the effective bandwidth is restricted and hard to meet the wire speed storage requirement of the high-end communication devices.